class simple_response_seq extends uvm_sequence #(apb_transfer);
     // ...
     virtual task body();
	`uvm_info(get_type_name(), "Starting...", UVM_MEDIUM)
	forever begin
	   p_sequencer.addr_trans_port.peek(util_transfer);
	   // ...
	end
     endtask : body
  endclass : simple_response_seq

  class apb_slave_sequencer extends uvm_sequencer #(apb_transfer);
     // ...
     uvm_blocking_peek_port#(apb_transfer) addr_trans_port;
     // ...
  endclass : apb_slave_sequencer

  class apb_monitor extends uvm_monitor;
     // ...
     // Allows the sequencer to look at monitored data for responses
    uvm_blocking_peek_imp#(apb_transfer,apb_monitor) addr_trans_export;

    // Allows monitor to look at collector for address information
    uvm_blocking_peek_port#(apb_transfer) addr_trans_port;

    event trans_addr_grabbed;
  endclass : apb_monitor

    // UVM run_phase
  task apb_monitor::run_phase(uvm_phase phase);
    forever begin
      addr_trans_port.peek(trans_collected);
      `uvm_info(get_type_name(), $sformatf("Address Phase Complete: %h[%s]", trans_collected.addr, trans_collected.direction.name() ), UVM_HIGH)
      -> trans_addr_grabbed;
    end
  endtask : run_phase

  // FUNCTION: peek - Allows the sequencer to peek at monitor for responses
  task apb_monitor::peek(output apb_transfer trans);
    @trans_addr_grabbed;
    trans = trans_collected;
  endtask : peek

  class apb_collector extends uvm_component;
     // ...
     // TLM Port - Allows sequencer access to transfer during address phase
    uvm_blocking_peek_imp#(apb_transfer,apb_collector) addr_trans_export;
    event addr_trans_grabbed;
  endclass : apb_collector

     // UVM run_phase()
  task apb_collector::run_phase(uvm_phase phase);
      @(posedge vif.preset);
      `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)
      collect_transactions();
  endtask : run_phase

  // collect_transactions
  task apb_collector::collect_transactions();
    forever begin
      @(posedge vif.pclock iff (vif.psel != 0));
      void'(this.begin_tr(trans_collected,"APB_COLLECTOR","UVM Debug","APB collector transaction inside collect_transactions()"));
      trans_collected.addr = vif.paddr;
      trans_collected.master = cfg.master_config.name;
      trans_collected.slave = cfg.get_slave_name_by_addr(trans_collected.addr);
      case (vif.prwd)
	1'b0 : trans_collected.direction = APB_READ;
	1'b1 : trans_collected.direction = APB_WRITE;
      endcase
	@(posedge vif.pclock);
      if(trans_collected.direction == APB_READ)
	trans_collected.data = vif.prdata;
      if (trans_collected.direction == APB_WRITE)
	trans_collected.data = vif.pwdata;
      -> addr_trans_grabbed;
      @(posedge vif.pclock);
      if(trans_collected.direction == APB_READ) begin
	  if(vif.pready != 1'b1)
	    @(posedge vif.pclock);
	trans_collected.data = vif.prdata;
	end
      this.end_tr(trans_collected);
      item_collected_port.write(trans_collected);
      `uvm_info(get_type_name(), $sformatf("Transfer collected :\n%s",
		trans_collected.sprint()), UVM_MEDIUM)
	`ifdef HEAP
	runq.push_back(trans_collected);
	`endif
       num_transactions++;
      end
  endtask : collect_transactions

  task apb_collector::peek(output apb_transfer trans);
    @addr_trans_grabbed;
    trans = trans_collected;
  endtask : peek

  // UVM connect_phase
  function void apb_env::connect_phase(uvm_phase phase);
    super.connect_phase(phase);
    // Get the virtual interface if set via get_config
    if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
      `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
    bus_collector.item_collected_port.connect(bus_monitor.coll_mon_port);
    bus_monitor.addr_trans_port.connect(bus_collector.addr_trans_export);
    master.monitor = bus_monitor;
    master.collector = bus_collector;
    foreach(slaves[i]) begin
      slaves[i].monitor = bus_monitor;
      slaves[i].collector = bus_collector;
      if (slaves[i].is_active == UVM_ACTIVE)
	slaves[i].sequencer.addr_trans_port.connect(bus_monitor.addr_trans_export);
    end
  endfunction : connect_phase

module fanout (/*AUTOARG*/)
   input i;
   output [31:0] o;
   wire [31:0] o = {32{i}};
endmodule

module fanout (/*AUTOARG*/
   // Outputs
   o,
   // Inputs
   i
   )
   input i;
   output [31:0] o;
   wire [31:0] o = {32{i}};
endmodule

module ex_inst (/*AUTOARG*/)
   input i;
   output [31:0] o;
   inout      io;

   fanout fanout (/*AUTOINST*/);
endmodule

module ex_inst (/*AUTOARG*/
   // Outputs
   o,
   // Inouts
   io,
   // Inputs
   i
   )
   input i;
   output [31:0] o;
   inout      io;

   fanout fanout (/*AUTOINST*/
	  // Outputs
	  .o            (o[31:0]),
	  // Inputs
	  .i            (i));
endmodule

__PACKAGE__->has_many(
  "blog_tags",
  "Schema::Result::BlogTag",
  { "foreign.blog" => "self.id" },
  { cascade_copy => 0, cascade_delete => 0 },
);

__PACKAGE__->belongs_to(
  "blog",
  "Schema::Result::Blog",
  { id => "blog" },
  { is_deferrable => 1, on_delete => "CASCADE", on_update => "CASCADE" },
);

__PACKAGE__->belongs_to(
  "blog",
  "Schema::Result::Blog",
  { "foreign.id" => "self.blog" },
  { is_deferrable => 1, on_delete => "CASCADE", on_update => "CASCADE" },
);

sqlite3 test.db

package abc;
use strict;
use warnings;

$VERSION = 0.1;

sub get_ver {$VERSION}

package main;
print "step 1: $abc::VERSION\n";
print "step 2: ". abc::get_ver();

Global symbol "$VERSION" requires explicit package name (did you forget to declare "my $VERSION"?) at a.pl line 7.
Global symbol "$VERSION" requires explicit package name (did you forget to declare "my $VERSION"?) at a.pl line 10.
Execution of a.pl aborted due to compilation errors.

package abc;
use strict;
use warnings;

$abc::VERSION = 0.1;

sub get_ver {$abc::VERSION}

package main;
print "step 1: $abc::VERSION\n";
print "step 2: ". abc::get_ver();

package abc;
use strict;
use warnings;

our $VERSION = 0.1;

sub get_ver {$VERSION}

package main;
print "step 1: $abc::VERSION\n";
print "step 2: ". abc::get_ver();

`uvm_info("ID0", "this is debug message", UVM_DEBUG)
`uvm_info("ID1", "this is full message", UVM_FULL)
`uvm_info("ID2", "this is high message", UVM_HIGH)
`uvm_info("ID3", "this is medium message", UVM_MEDIUM)
`uvm_info("ID4", "this is low message", UVM_LOW)
`uvm_info("ID5", "this is none message", UVM_NONE)

+uvm_set_verbosity=component_name,id,verbosity,phase_name,optional_time

+uvm_set_action=component,id,severity,action

class bad_transaction extends transaction;
  bit bad;

function new(string name);
  super.new(name);
  bad = 1;
endfunction

endclass

class bad_sequence extends sequence;
  bad_transaction m_bad_transaction;
function new(string name);
  super.new(name);
  m_bad_transaction = bad_transaction::new("m_bad_transaction"); 
endfunction


endclass

class bad_driver extends driver;
bad_transaction m_bad_transaction;
...
endclass

uvm_factory -override -by_type transaction bad_transaction 

class transaction extends uvm_sequence_item;
  `uvm_object_utils(transaction)
  ...
endclass

class bad_transaction extends transaction;
  `uvm_object_utils(bad_transaction)
  bit bad;

function new(string name);
  super.new(name);
  bad = 1;
endfunction

endclass

class sequence extends uvm_sequence;
  transaction m_transaction;
function new(string name);
  super.new(name);
  m_transaction = transaction::type_id::create("m_transaction");
endfunction

endclass

// translation sequence type
typedef uvm_reg_sequence #(uvm_sequence #(apb_rw)) reg2apb_seq_t;

class block_env extends uvm_env;
  block_reg_model regmodel;
  uvm_sequencer#(uvm_reg_item) reg_seqr;
  apb_agent apb;
  reg2apb_seq_t reg2apb_seq;

  virtual function void connect();
    if (regmodel.get_parent() == null) begin
      regmodel.default_map.set_sequencer(reg_seqr,null);
      reg2apb_seq = reg2apb_seq_t::type_id::create("reg2apb_seq",,get_full_name());
      reg2apb_seq.reg_seqr = reg_seqr;
      reg2apb_seq.adapter =
      reg2apb_adapter::type_id::create("reg2apb",,get_full_name());
      regmodel.set_auto_predict(1);
    end
  endfunction

  virtual task run();
    reg2apb_seq.start(apb.sequencer);
  endtask
endclass

class my_test extends uvm_test;
  block_env env;
  virtual function void run();
    my_reg_sequence seq = my_reg_sequence::type_id::create("seq",this);
    seq.start(env.reg_seqr);
  endfunction
endclass

class wifi_t extends uvm_reg_block;
...
  uvm_reg_map wifi_top;
  uvm_reg_map UnAddressedModules;
...
  virtual function void build();
    wifi_top = create_map("wifi_top", 'h0, 4, UVM_LITTLE_ENDIAN, 1);
    UnAddressedModules = create_map("UnAddressedModules", 'h0, 4, UVM_LITTLE_ENDIAN, 1);
    default_map = wifi_top;
...    
endclass

virtual function void build_phase(uvm_phase phase);
    reg_seqr = uvm_sequencer#(uvm_reg_item)::type_id::create("reg_seqr", this);

    rdb = wifi_t::type_id::create("rdb", this);
    rdb.configure(null,"");
    rdb.build();
    rdb.reset();
    rdb.lock_model();
  endfunction

  virtual function void connect_phase(uvm_phase phase);
    super.connect_phase(phase);

    vsequencer.ahb_master_sqr = ahb_master_uvc.sequencer;
    vsequencer.reg_seqr       = reg_seqr;
    rdb.default_map.set_sequencer(vsequencer.ahb_master_sqr, reg2ahb);
    rdb.default_map.set_auto_predict(1);

    rdb.UnAddressedModules.set_sequencer(reg_seqr,null); // note that do not set adapter here
    rdb.UnAddressedModules.set_auto_predict(1);

    reg_tl_seq = reg_tl_seq_t::type_id::create("reg_tl_seq",,get_full_name());
    req_tl_seq.reg_seqr = reg_seqr; // set upstream sequencer
    req_tl_seq.rdb = this.rdb;
    req_tl_seq.adapter = reg2ahb;
    reg_tl_seq.phy_bank_cfg = env_cfg.phy_bank_cfg;

  endfunction

  virtual task main_phase(uvm_phase phase);
    super.main_phase(phase);
    env_cfg.print();
    reg_tl_seq.start(vsequncer.ahb_master_sqr);
  endtask

virtual task body();
    ...
    forever begin
      uvm_reg_item reg_item;
      reg_seqr.peek(reg_item);
      do_reg_item(reg_item);
      reg_seqr.get(reg_item);
      #0;
    end
  endtask

virtual task body();
  ...
  forever begin
    uvm_reg_item req;
    reg_seqr.peek(req);
    select_bank(0);
    if (req.kind == UVM_READ) begin
      read_data(req);
    end
    else begin
      write_data(req);
    end
    reg_seqr.get(req);
    #0;
    req.end_tr();
  end

task uvm_reg_map::do_write(uvm_reg_item rw);
  ...
  rw.parent.start_item(rw,rw.prior);
  rw.parent.finish_item(rw);
  rw.end_event.wait_on();// wait rw to be consumed
endtask

{
    "timescale":"1ns/1ps",
    "dut":{
	"name":"mydut",
	"top_file":"~/mydut.v",
	"filelist":"~/mydut.f"
    },
    "tbp":"demo",
    "env":{
	"name":"bus",
	"agent":[
	    {
		"name":"abc",
		"active":1,
		"off":0,
		"interface":{
		    "ifclk":"clk",
		    "ifrst":"rst",
		    "signal":[
			{
			    "name":"ahb_burst",
			    "bind":"ahb_burst_o"
			},
			{
			    "name":"ahb_valid",
			    "bind":"ahb_valid_o"
			}
		    ]
		}
	    }
	]
    }   
}

{
    "type": "object",
    "properties":{
	"timescale":{
	    "type": "string"
	},
	"dut":{
	    "type":"object",
	    "properties":{
		"name":{
		    "type":"string"
		},
		"top_file":{
		    "type":"string"
		},
		"filelist":{
		    "type":"string"
		}
	    },
	    "required":["name","top_file","filelist"]
	},
	"env":{
	    "type":"object",
	    "properties":{
		"name":{
		    "type":"string"
		},
		"agent":{
		    "type":"array",
		    "items":{
			"type":"object",
			"properties":{
			    "name":{
				"type":"string"
			    },
			    "active":{
				"type":"integer"
			    },
			    "off":{
				"type":"integer"
			    },
			    "interface":{
				"type":"object",
				"properties":{
				    "ifclk":{
					"type":"string"
				    },
				    "ifrst":{
					"type":"string"
				    },
				    "signal":{
					"type":"array",
					"items":{
					    "type":"object",
					    "properties":{
						"name":{
						    "type":"string"
						},
						"bind":{
						    "type":"string"
						}
					    },
					    "required":["name"]
					},
					"minItems":1
				    }
				},
				"required":["signal"]
			    }
			},
			"required":["name"]
		    },
		    "minItems":1
		}
	    }
	}			
    },
    "required":["dut"]
}

use JSON qw(decode_json);
use JSON::Validator qw(validate_json);

my $validator = JSON::Validator->new;

open(FILE, "top.schema.json") or die "Can not open file top.schema.json";
my @lines = <FILE>;

my $schema = decode_json(join("\n",@lines));

close(FILE); 
$validator->schema($schema);

open(FILE, "cfg.json") or die "Can not open file cfg.json";
@lines = <FILE>;
close(FILE);
my $json_to_be_validated = decode_json(join("\n",@lines));

# Validate your data
@errors = $validator->validate($json_to_be_validated);

# Do something if any errors was found
die "@errors" if @errors;

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE top
SYSTEM "top.dtd.xml"
>
  <top>
    <timescale value="1ns/1ps" />
    <dut name="mydut" top_file="~/mydut.v" filelist="~/mydut.f" />
    <tbp name="demo" />
    <env name="bus" >
      <agent name="abc" active="1" off="0" >
	<interface name="aa" >
	  <ifclk name="clk" />
	  <ifrst name="rst" />
	  <signal name="ahb_burst" bind="ahb_burst_o" />
	  <signal name="ahb_valid" bind="ahb_valid_o" />
	</interface>
      </agent>
    </env>
  </top>

<?xml version="1.0" encoding="UTF-8" ?>
  <!-- The top tag is the root tag. -->
<!ELEMENT top (timescale?,dut,tbp?,env) >

<!ELEMENT timescale EMPTY >
  <!ATTLIST timescale value CDATA #REQUIRED>

<!ELEMENT dut EMPTY>
  <!ATTLIST dut name CDATA #REQUIRED>
  <!ATTLIST dut top_file CDATA #REQUIRED>
  <!ATTLIST dut filelist CDATA #REQUIRED>


<!ELEMENT tbp EMPTY>
  <!ATTLIST tbp name CDATA #REQUIRED>

<!ELEMENT env (agent+)>
  <!ATTLIST env name CDATA #REQUIRED>

<!ELEMENT agent (interface)>
  <!ATTLIST agent name CDATA #REQUIRED>
  <!ATTLIST agent active CDATA #REQUIRED>
  <!ATTLIST agent off CDATA #REQUIRED>

<!ELEMENT interface (ifclk*,ifrst*,signal+)>
  <!ATTLIST interface name CDATA #REQUIRED>

<!ELEMENT ifclk EMPTY>
  <!ATTLIST ifclk name CDATA #REQUIRED>

<!ELEMENT ifrst EMPTY>
  <!ATTLIST ifrst name CDATA #REQUIRED>

<!ELEMENT signal EMPTY>
  <!ATTLIST signal name CDATA #REQUIRED>
  <!ATTLIST signal bind CDATA #IMPLIED>

use XML::LibXML;

my $parser = XML::LibXML->new;

$parser->validation(1);

$parser->parse_file("cfg.xml");